module tb_wrr;
parameter N = 8;
reg  clk, rst_n;
reg  [N-1:0] req;
wire [N-1:0] grant;

initial begin
    clk = 0;
    forever begin
        #5 clk = ~clk;
    end
end

initial begin
    rst_n = 0;
    repeat(2)@(posedge clk);
    @(negedge clk);
    rst_n = 1;
end

task tx;
    input [7:0] data;
    @(posedge clk);
    #2 req = data;
endtask
//targeted case : rr_arbiter behavior
initial begin
   req = 8'd0;
   @(posedge rst_n);
   tx(8'b1111_1111);
   tx(8'b1111_1110);
   tx(8'b1111_1100);
   tx(8'b1111_1000);
   tx(8'd0);
   tx(8'd0);
   tx(8'b1111_0000);
   tx(8'b1110_0000);
   tx(8'd0);
   tx(8'b1100_0000);
   tx(8'b1000_0000);
   #50;
   repeat(100)begin
        tx(8'b1111_1111);
    end
   $stop;
end
/*
initial begin
    req = 8'd0;
    @(posedge rst_n);
    repeat(70)begin
        tx(8'b1111_1111);
    end
    repeat(3)@(posedge clk);
    $stop;
end
*/
initial begin
    $fsdbDumpfile("tb_wrr.fsdb");
    $fsdbDumpvars(0,tb_wrr);
end

wrr_arbiter #(.N (N)) u_wrr(
    .clk    (clk),
    .rst_n  (rst_n),
    .req    (req),
    .grant  (grant)
);

endmodule


    
        
